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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">cy_stc_dpll_hp_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__sysclk.html">SysClk       (System Clock)</a> &raquo; <a class="el" href="group__group__sysclk__pll.html">Phase Locked Loop (PLL)</a> &raquo; <a class="el" href="group__group__sysclk__pll__structs.html">Data Structures</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Structure containing information for configuration of a DPLL-HP. </p>
<dl class="section note"><dt>Note</dt><dd>This structure is available only for CAT1D devices. </dd></dl>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a641a2165833046cdd23c8b0048cd22be"><td class="memItemLeft" align="right" valign="top"><a id="a641a2165833046cdd23c8b0048cd22be"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a641a2165833046cdd23c8b0048cd22be">nDiv</a></td></tr>
<tr class="memdesc:a641a2165833046cdd23c8b0048cd22be"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG register, NDIV bits, Ratio between DCO frequency and reference frequency. <br /></td></tr>
<tr class="separator:a641a2165833046cdd23c8b0048cd22be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a811133849a399ceb7d3d1f14cabb9724"><td class="memItemLeft" align="right" valign="top"><a id="a811133849a399ceb7d3d1f14cabb9724"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a811133849a399ceb7d3d1f14cabb9724">pDiv</a></td></tr>
<tr class="memdesc:a811133849a399ceb7d3d1f14cabb9724"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG register, PDIV bits, Pre-Divider for scaling the reference frequency. <br /></td></tr>
<tr class="separator:a811133849a399ceb7d3d1f14cabb9724"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac070b4097282b837558c094f5ae03cbe"><td class="memItemLeft" align="right" valign="top"><a id="ac070b4097282b837558c094f5ae03cbe"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#ac070b4097282b837558c094f5ae03cbe">kDiv</a></td></tr>
<tr class="memdesc:ac070b4097282b837558c094f5ae03cbe"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG register, KDIV bits, Post-Divider. <br /></td></tr>
<tr class="separator:ac070b4097282b837558c094f5ae03cbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a842c51612a652668407405b768852d5f"><td class="memItemLeft" align="right" valign="top"><a id="a842c51612a652668407405b768852d5f"></a>
<a class="el" href="group__group__sysclk__fll__enums.html#ga777e08424e26c9cd8c2602b2114e716b">cy_en_fll_pll_output_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a842c51612a652668407405b768852d5f">outputMode</a></td></tr>
<tr class="memdesc:a842c51612a652668407405b768852d5f"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG register, BYPASS_SEL bits. <br /></td></tr>
<tr class="separator:a842c51612a652668407405b768852d5f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac175c480121f5a6be6b90032b7b53600"><td class="memItemLeft" align="right" valign="top"><a id="ac175c480121f5a6be6b90032b7b53600"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#ac175c480121f5a6be6b90032b7b53600">pllEn</a></td></tr>
<tr class="memdesc:ac175c480121f5a6be6b90032b7b53600"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG register, ENABLE bits, Master Enable for PLL. <br /></td></tr>
<tr class="separator:ac175c480121f5a6be6b90032b7b53600"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a275a2371308891194efd7d2a3cc92999"><td class="memItemLeft" align="right" valign="top"><a id="a275a2371308891194efd7d2a3cc92999"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a275a2371308891194efd7d2a3cc92999">nDivFract</a></td></tr>
<tr class="memdesc:a275a2371308891194efd7d2a3cc92999"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG2 register, NDIV_FRACT bits, N-divider division factor. <br /></td></tr>
<tr class="separator:a275a2371308891194efd7d2a3cc92999"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5fb8e4952c2e10b0fc0e0460c538d9a4"><td class="memItemLeft" align="right" valign="top"><a id="a5fb8e4952c2e10b0fc0e0460c538d9a4"></a>
<a class="el" href="group__group__sysclk__pll__structs.html#gaf99eec425e4a077026c29fca5f2e7f47">cy_en_wait_mode_select_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a5fb8e4952c2e10b0fc0e0460c538d9a4">freqModeSel</a></td></tr>
<tr class="memdesc:a5fb8e4952c2e10b0fc0e0460c538d9a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG2 register, MODE_SEL bits, Selects the waiting time for Power Initialization sequence. <br /></td></tr>
<tr class="separator:a5fb8e4952c2e10b0fc0e0460c538d9a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab05cabef07016629b545a41b4f9dcaf3"><td class="memItemLeft" align="right" valign="top"><a id="ab05cabef07016629b545a41b4f9dcaf3"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#ab05cabef07016629b545a41b4f9dcaf3">ivrTrim</a></td></tr>
<tr class="memdesc:ab05cabef07016629b545a41b4f9dcaf3"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG2 register, IVR_TRIM bits, Trim value for the Regulated Voltage. <br /></td></tr>
<tr class="separator:ab05cabef07016629b545a41b4f9dcaf3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5e4d73a8e3bfc0593e40dfff746e5733"><td class="memItemLeft" align="right" valign="top"><a id="a5e4d73a8e3bfc0593e40dfff746e5733"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a5e4d73a8e3bfc0593e40dfff746e5733">clkrSel</a></td></tr>
<tr class="memdesc:a5e4d73a8e3bfc0593e40dfff746e5733"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG3 register, CLKR_SEL bit, Select re-timed reference clock. <br /></td></tr>
<tr class="separator:a5e4d73a8e3bfc0593e40dfff746e5733"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a02b460a4b234e130824a30cf0c655a6d"><td class="memItemLeft" align="right" valign="top"><a id="a02b460a4b234e130824a30cf0c655a6d"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a02b460a4b234e130824a30cf0c655a6d">fdsmSel</a></td></tr>
<tr class="memdesc:a02b460a4b234e130824a30cf0c655a6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG3 register, FDSM_SEL bit, DSM clock division select, true - div_by_2, false - div_by_4. <br /></td></tr>
<tr class="separator:a02b460a4b234e130824a30cf0c655a6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac8b58bc445f7d57fff98101f4d3e7fad"><td class="memItemLeft" align="right" valign="top"><a id="ac8b58bc445f7d57fff98101f4d3e7fad"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#ac8b58bc445f7d57fff98101f4d3e7fad">alphaCoarse</a></td></tr>
<tr class="memdesc:ac8b58bc445f7d57fff98101f4d3e7fad"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, LF_LC_ALPHA bits, Alpha value of the coarse filter. <br /></td></tr>
<tr class="separator:ac8b58bc445f7d57fff98101f4d3e7fad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0678d84bd2bdcf02dac9e07182be7cd"><td class="memItemLeft" align="right" valign="top"><a id="aa0678d84bd2bdcf02dac9e07182be7cd"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#aa0678d84bd2bdcf02dac9e07182be7cd">betaCoarse</a></td></tr>
<tr class="memdesc:aa0678d84bd2bdcf02dac9e07182be7cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, LF_LC_BETA bits, Beta value of the coarse filter. <br /></td></tr>
<tr class="separator:aa0678d84bd2bdcf02dac9e07182be7cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1c884c496ded8f3e390812b471cf55b7"><td class="memItemLeft" align="right" valign="top"><a id="a1c884c496ded8f3e390812b471cf55b7"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a1c884c496ded8f3e390812b471cf55b7">flockThresh</a></td></tr>
<tr class="memdesc:a1c884c496ded8f3e390812b471cf55b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, FLOCK_EN_THRESH bits, PQDIFF threshold under which FINE Filtering gets enabled. <br /></td></tr>
<tr class="separator:a1c884c496ded8f3e390812b471cf55b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade71fd9cf93c4e56fe31b23050ef6c68"><td class="memItemLeft" align="right" valign="top"><a id="ade71fd9cf93c4e56fe31b23050ef6c68"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#ade71fd9cf93c4e56fe31b23050ef6c68">flockWait</a></td></tr>
<tr class="memdesc:ade71fd9cf93c4e56fe31b23050ef6c68"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, FLOCK_WAITPER bits, Period over which flock_en_thresh must be met in order for FINE Filtering enabling. <br /></td></tr>
<tr class="separator:ade71fd9cf93c4e56fe31b23050ef6c68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9437db183b33c88c4d66638198edda6b"><td class="memItemLeft" align="right" valign="top"><a id="a9437db183b33c88c4d66638198edda6b"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a9437db183b33c88c4d66638198edda6b">flockLkThres</a></td></tr>
<tr class="memdesc:a9437db183b33c88c4d66638198edda6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, FLOCK_LK_THRESH bits, PQDIFF threshold under which DLL asserts Freq LOCK. <br /></td></tr>
<tr class="separator:a9437db183b33c88c4d66638198edda6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a169e8c959c142babc49a0cdf5e528329"><td class="memItemLeft" align="right" valign="top"><a id="a169e8c959c142babc49a0cdf5e528329"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a169e8c959c142babc49a0cdf5e528329">flockLkWait</a></td></tr>
<tr class="memdesc:a169e8c959c142babc49a0cdf5e528329"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, FLOCK_LK_WAITPER bits, Period over which flock_en_thresh must be met in order for Freq Locking. <br /></td></tr>
<tr class="separator:a169e8c959c142babc49a0cdf5e528329"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aba2697b384d1386496dd1d7a6ef83468"><td class="memItemLeft" align="right" valign="top"><a id="aba2697b384d1386496dd1d7a6ef83468"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#aba2697b384d1386496dd1d7a6ef83468">flockObs</a></td></tr>
<tr class="memdesc:aba2697b384d1386496dd1d7a6ef83468"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, FLOCK_OBSWIN bits, Period over which PQDIFF is computed/observed. <br /></td></tr>
<tr class="separator:aba2697b384d1386496dd1d7a6ef83468"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3347f5dd8f1daa9be0e54ba945beac8c"><td class="memItemLeft" align="right" valign="top"><a id="a3347f5dd8f1daa9be0e54ba945beac8c"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a3347f5dd8f1daa9be0e54ba945beac8c">alphaExt</a></td></tr>
<tr class="memdesc:a3347f5dd8f1daa9be0e54ba945beac8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG5 register, LF_ALPHA bits, External Alpha value. <br /></td></tr>
<tr class="separator:a3347f5dd8f1daa9be0e54ba945beac8c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a058003220283c3ee8fa9d78c1c278f46"><td class="memItemLeft" align="right" valign="top"><a id="a058003220283c3ee8fa9d78c1c278f46"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a058003220283c3ee8fa9d78c1c278f46">betaExt</a></td></tr>
<tr class="memdesc:a058003220283c3ee8fa9d78c1c278f46"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG5 register, LF_BETA bits, External Beta value. <br /></td></tr>
<tr class="separator:a058003220283c3ee8fa9d78c1c278f46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a15121419c601cb438eb055b0ad983043"><td class="memItemLeft" align="right" valign="top"><a id="a15121419c601cb438eb055b0ad983043"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a15121419c601cb438eb055b0ad983043">lfEn</a></td></tr>
<tr class="memdesc:a15121419c601cb438eb055b0ad983043"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG5 register, LF_SET_PARAMS bit, enable for external loop filter control (alpha and beta values) <br /></td></tr>
<tr class="separator:a15121419c601cb438eb055b0ad983043"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aadb0a58406c26720d4042f957aa53b83"><td class="memItemLeft" align="right" valign="top"><a id="aadb0a58406c26720d4042f957aa53b83"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#aadb0a58406c26720d4042f957aa53b83">dtCal</a></td></tr>
<tr class="memdesc:aadb0a58406c26720d4042f957aa53b83"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG5 register, DUTY CAL circuit status. <br /></td></tr>
<tr class="separator:aadb0a58406c26720d4042f957aa53b83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aed5d049a18be6c46e61611050cb96226"><td class="memItemLeft" align="right" valign="top"><a id="aed5d049a18be6c46e61611050cb96226"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#aed5d049a18be6c46e61611050cb96226">tmodFreq</a></td></tr>
<tr class="memdesc:aed5d049a18be6c46e61611050cb96226"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRIGMOD register, TRIMOD_FREQ bits, Triangular-Frequency Modulation: modulation frequency. <br /></td></tr>
<tr class="separator:aed5d049a18be6c46e61611050cb96226"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa5026edf356536232e6e8117ce59da6e"><td class="memItemLeft" align="right" valign="top"><a id="aa5026edf356536232e6e8117ce59da6e"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#aa5026edf356536232e6e8117ce59da6e">tmodGrad</a></td></tr>
<tr class="memdesc:aa5026edf356536232e6e8117ce59da6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRIGMOD register, TRIMOD_GRD bits, Triangular-Frequency Modulation: modulation gradient. <br /></td></tr>
<tr class="separator:aa5026edf356536232e6e8117ce59da6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a63143c43e5e88d3ef3af9ca20a191bac"><td class="memItemLeft" align="right" valign="top"><a id="a63143c43e5e88d3ef3af9ca20a191bac"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a63143c43e5e88d3ef3af9ca20a191bac">tmodRate</a></td></tr>
<tr class="memdesc:a63143c43e5e88d3ef3af9ca20a191bac"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRIGMOD2 register, TRIMOD_RATE bits, Triangular-Frequency Modulation Rate. <br /></td></tr>
<tr class="separator:a63143c43e5e88d3ef3af9ca20a191bac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abead82f3d74d3663a874572cf91bab71"><td class="memItemLeft" align="right" valign="top"><a id="abead82f3d74d3663a874572cf91bab71"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#abead82f3d74d3663a874572cf91bab71">tmodEn</a></td></tr>
<tr class="memdesc:abead82f3d74d3663a874572cf91bab71"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRIGMOD2 register, TRIMOD_EN bit, Triangular-Frequency Modulation enable. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a28fab45dc91ea11ae572d1be64117a5c">tmodStop</a></td></tr>
<tr class="memdesc:a28fab45dc91ea11ae572d1be64117a5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRIGMOD2 register, TRIMOD_STP bit, Triangular-Frequency Modulation stop. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#ad0930c68079419eebfd8f0cecd96feed">pllLocked</a></td></tr>
<tr class="memdesc:ad0930c68079419eebfd8f0cecd96feed"><td class="mdescLeft">&#160;</td><td class="mdescRight">STATUS register, LOCKED bits, PLL Lock Indicator. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a6755fda17601b2e5f207608fed7b77b5">pllUnlock</a></td></tr>
<tr class="memdesc:a6755fda17601b2e5f207608fed7b77b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">STATUS register, UNLOCK_OCCURRED bit, Sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a298368708777b65225ec1958fa18e3e8">lockDetReset</a></td></tr>
<tr class="memdesc:a298368708777b65225ec1958fa18e3e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">STATUS register, LOCKDET_RES bit, Restart lock detector. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a69d5bf7a08aecaf2da127266af392c5d">lockDetRstAck</a></td></tr>
<tr class="memdesc:a69d5bf7a08aecaf2da127266af392c5d"><td class="mdescLeft">&#160;</td><td class="mdescRight">STATUS register, LOCKDET_RES_ACK bit, Acknowledgement for lock detection restart. <br /></td></tr>
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uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#aca218a9f8fde35974770de04d335ba6a">dcCalDelta</a></td></tr>
<tr class="memdesc:aca218a9f8fde35974770de04d335ba6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DUTYCAL_CTRL register, DELTA bits, Margins for the duty cycle calibration error. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#ac6f53dac0879174b6914dfe851b871f5">dcRatioStatus</a></td></tr>
<tr class="memdesc:ac6f53dac0879174b6914dfe851b871f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">DUTYCAL_CTRL register, RATIO_OK bit, Status of the duty calibration ratio. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a0e7587835728396505ce2f3cc91c224a">dcStatus</a></td></tr>
<tr class="memdesc:a0e7587835728396505ce2f3cc91c224a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DUTYCAL_CTRL register, OK bit, Status of the duty calibration. <br /></td></tr>
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uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#aa73020d6a06f6796f56aa2062bfde74d">dcTarget</a></td></tr>
<tr class="memdesc:aa73020d6a06f6796f56aa2062bfde74d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DUTYCAL_CTRL register, TARGET bits, Duty cycle target. <br /></td></tr>
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<tr class="memitem:a7f14358f562bc77615cdfbe362a4ebb1"><td class="memItemLeft" align="right" valign="top"><a id="a7f14358f562bc77615cdfbe362a4ebb1"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a7f14358f562bc77615cdfbe362a4ebb1">dcEnRingOsc</a></td></tr>
<tr class="memdesc:a7f14358f562bc77615cdfbe362a4ebb1"><td class="mdescLeft">&#160;</td><td class="mdescRight">DUTYCAL_CTRL register, CTRL_RG_EN bit, Enables ring oscillator for duty cycle digitization. <br /></td></tr>
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<tr class="memitem:a96487d71c2ba8a64281cdc418556a6cd"><td class="memItemLeft" align="right" valign="top"><a id="a96487d71c2ba8a64281cdc418556a6cd"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__hp__config__t.html#a96487d71c2ba8a64281cdc418556a6cd">dcEn</a></td></tr>
<tr class="memdesc:a96487d71c2ba8a64281cdc418556a6cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">DUTYCAL_CTRL register, EN bit, Enables duty cycle calibration. <br /></td></tr>
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